"FT-EA"

"Using Fault-Tolerance techniques to combat Electrical Aspects in deep sub micron IC Technology"

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Summary

Summary of the "FT-EA" project:

 

The objectives

Our ambition with this project proposal is to achieve a single coding/decoding scheme, which is capable of tackling not only the preliminary fault tolerance, but all important issues in bus communication. We want to analyse the different electrical issues one by one to finally arrive at a complete insight and unified approach. We expect that this revolutionary approach to combat electrical problems can achieve a lot more than we already found, on unexpected fields and with good improvements We should note that the gaining's are completely for free, as the codes need to be implemented for fault tolerance anyway.

 

The work plan

Our ambition is to achieve a Fault Tolerance coding/decoding scheme for error correction in integrated circuits, which not only corrects the errors on the chip but is also capable of tackling important issues in bus communication such as power consumption and noise. We will analyse the different electrical issues one by one to finally arrive at a complete insight and a unified approach. First we investigate the benefits of fault-tolerant coding to reduce energy consumption. Next, cross talk effects will be investigated. Finally the effects on simultaneously switching outputs (ground bounce) will be investigated. For the latter we will focus on memories and microprocessors. This result might be applicable for worldwide standardisation.