1.    Introduction

The SMASH storage device is drawn up as a server for multimedia applications in the home. A lot of different data type like text, graphics, digital audio and video sequences can be stored on this device. The combo itself has no user interface and will be complete remote controlled. All these information has to be transported with help of the Interconnection System of the SMASH Combo, which is specified below.


2.    Standardized Interconnect System

2.1    Applicable Standards
The interface for the SMASH storage device is based fundamentally on two standards:

IEC 61883/FDIS CONSUMER AUDIO/VIDEO EQUIPMENT- DIGITAL INTERFACE

IEEE 1394-1994 Standard for a High Performance Serial Bus

The characteristics and behavior of the open interface for the SMASH storage device shall comply to these standards if there are no qualifications and limitations described in this document.

2.2    Layered Structure of the Interface
The interface of the SMASH storage device can be divided in different layers. The different layers of the interconnect system are depicted in figure 1.
The Bus Management, Transaction, Link and Physical Layer are standardized in IEEE 1394-1995. The AV Layer is subject of the IEC 61886 standard.

Figure 1 Layered Structure of the SMASH Interconnect System

2.3    Specification of the Physical Layer
The specification of the Physical Layer for the SMASH storage device refers to the "Cable Phy Specification" described in chapter 6 of the IEEE 1394-1995 standard.

2.3.1    Number of Ports
The SMASH device shall have one node with a minimum number of two ports. Additional ports are optional.

2.3.2    Connector socket type
The two mandatory ports shall have 6-pin connectors in accordance to chapter 4.2.1.1.3 of IEEE 1394-1995. Additional ports may have either 6 pin connectors or 4-pin connectors described in Annex A of the IEC 61883-1/FDIS.

                  Figure 2 6-pin connector IEEE 1394-1995                                    4 pin-connector IEC 61883 Annex A

2.3.3    Cable Power Requirements
The SMASH device shall not operate as a power sink. The operation as power source is optional. The corresponding POWER_CLASS has to be attached in the Self-ID packet.

2.3.4    Data Rate
The interface has to support the S100 cable media data rate of 98.304 Mbit/s ± 100ppm. The recommended data rate is S200 (196.608 Mbit/s ± 100ppm).

2.3.5    Isolation Requirements
An galvanic isolation between signal ground and power distribution ground is required to avoid leakage currents greater than 50 µA.

2.3.6    Cable Phy Packets
The Physical Layer of the SMASH device shall send and react of the receiving of SELF-ID PACKETS, LINK ON PACKETS and PHY CONFIGURATION PACKETS.

 

2.4    Specification of the Link Layer Capabilities

2.4.1    Packet Types
In accordance to the standard IEEE 1394-1995 chapter 6.2 shall the Link Layer of the SMASH storage device be able to process following packet types:

2.4.2    Cycle Time Register
To ensure the "Cycle Master" capability (see chapter 2.6), the Cycle Time Register has to be implemented. Additionally the Link Layer must be able to provide the time stamp, which is needed in the Source Packet Header for MPEG 2 Transport Stream transmission (see chapter 2.7.1.1) and the time stamp used in the SYT field of the CIP header for DVC transmission (see chapter 2.7.1.2). Both time stamps are derived from the Cycle Time Register contents.

2.4.3.    Isochronous Channel Support
The SMASH storage device shall support two isochronous channels (one outgoing, one incoming) simultaneously. Additional isochronous channel support is optional.

2.4.4    Maximum Isochronous Channel Bandwidth Requirements
Each channel of the interface shall support maximal 24.064 Mbit/s MPEG transport stream transmission or one DVC SD channel. The support of HD DVC and SDL DVC data transmission in accordance to IEC 61882 part 3 and part 5 are optional.

2.5    Transaction Layer

Every node should be transaction capable. The maximal size of a asynchronous packet should be 512 byte payload for both S100 and S200 speed. The value max_rec in the Configuration ROM is therefore set to 10002.
For write transaction is the use of a unified transaction recommended. For the Function Control Protocol (FCP) it is mandatory to use only the unified transaction.
Split transaction shall be supported.
Only the single phase retry mechanism is required to be supported.

2.6    Serial Bus Management Capability

The interface of the SMASH storage device shall have Isochronous Resource Manager capability.
The Interconnect System shall be able to provide Cycle Master capability.
Following Serial Bus node registers shall be implemented:

The STATE_CLEAR.cmstr has to be implemented.

The NODE_UNIQUE_ID shall be present in the BUS_INFO_BLOCK.

Following entries shall be implemented in the ROOT_DIRECTORY:

2.6.1    Configuration ROM

BUS_INFO_BLOCK

Name Value
irmc
12
cmc 12
isc 12
bmc 02 (12 optional)
cyc_clk_acc 100 ppm
max_rec 10002
node_vendor_id 24 bit company ID
chip_id 40 bit node unique ID

Table1 Assignment of Values in BUS_INFO_BLOCK

ROOT_DIRECTORY
The ROOT_DIRECTORY shall contain all mandatory data as described in chapter 5.3.3.2 of IEC 61883 part 1.

UNIT_DIRECTORY
The UNIT_DIRECTORY shall contain all mandatory data as described in chapter 5.3.3.3 of IEC 61883-1.

2.7   Audio and Video Layer

2.7.1    Real Time Data Transmission Protocol

In case of real time data transmission from or to the interface of the SMASH storage device, especially the transmitting of MPEG transport streams or DVC data, the "Real Time Data Transmission Protocol" in accordance to chapter 6 of IEC 61883 part 1 shall be used. The data has to be transmitted in isochronous packets described in chapter 6.2.3.1 of the IEEE 1394-1995 standard. The TAG field in the isochronous header shall be set to 012 as an indication that a Common Isochronous Packet (CIP) header will follow.

The structure of a CIP header is shown below:

 

               Figure 3 Format of Isochronous Common Packet Header

SID Source Node ID
DBS Data Block Size in quadlets
FN Fraction Number
QPC Quadlet Padding Count
SPH Source Packet Header present
DBC Data Block Continuity counter
FMT Format ID
FDF Format Dependent Field

              Table 2 Common Interface Packet Header Contents

2.7.1.1    Structure of Isochronous Packets for MPEG Transmission

Figure 4 Format of Isochronous Packts for MPEG TS Transmission

SID Source Node ID  
DBS Data Block Size in quadlets 000001102
FN Fraction Number XX2
QPC Quadlet Padding Count XX2
SPH Source Packet Header present 12
DBC Data Block Continuity counter 0 ... 255
FMT Format ID 1000002
FDF Format Dependent Field reserved

          Table 4 Common Interface Packet Header Contents for MPEG TS

Fractions of MPEG TS packets per 1394 packet are allowed with:

1/8 of a packet FN = 112 DBC increments with 1
¼ of a packet FN = 102 DBC increments with 2, LSB = 0
½ of a packet FN = 012 DBC increments with 4, LSBs = 002
N packets

N is an integer

FN = 112 DBC increments with 8, LSBs = 0002

         Table 5 Allowed Fractioning for MPEG Transport Strams

The time stamp in the SOURCE PACKET HEADER indicates the time of the CYCLE_TIME register, when the first bit on a transmitted MPEG transport packet has to be delivered to Transport Stream decoder. The SOURCE PACKET HEADER shall be generated in the sender of the interface by adding a appropriate value to current content of the CYCLE_TIME register. The low order 25 bits are used for the time stamp. The time stamp is necessary to eliminate the jitter added from the interface in the receiver.

Figure 5 Source packet Header for MPEG TS transmission

The interface shall transmit empty packets in those cycles if not enough data is available to transmit a Common Interface Packet in this cycle.
An overall view of transporting MPEG transport packets over the SMASH interface is shown in figure 6.

         Figure 6 Mapping of Transport Packets on Bus Packets

MPEG transport packets, which could not reach the target node within the in the source packet header indicated time shall be discarded at the transmitter (late packets).
In accordance to the in chapter 2.4.4 described maximum bandwidth for MPEG transmission, the interface shall provide minimal 3264 byte of buffer memory.

2.7.1.2    DVC Data Transmission

The transmission of SD DVC data from and to the SMASH storage device shall be compliant to IEC 61882 part 2. The appropriate CIP isochronous packet is shown in figure 7.

                   Figure 7 Common Interface Packet Header Contents for DVC

SID Source Node ID  
DBS Data Block Size in quadlets 011110002
FN Fraction Number 002
QPC Quadlet Padding Count 0002
SPH Source Packet Header present 02
DBC Data Block Continuity counter 0 ... 255
FMT Format ID 0000002
50/60 Fields System 50Hz = 1
STYPE Video Signal Type ("HD Flag") 000002 f. 525/625
000102 f. 1125/1250
SYT Video Frame Sync Time Stamp Cyc. Time f. frame start

                                 Table 6 Content of DVC CIP Header

2.7.1.3    Audio and Music Data Transmission

The support of Raw Audio, MIDI conformant and IEC 958 conformant audio data by the SMASH interconnect system is optional. If these kind of data is used by the storage device, the data format should be compliant to IEC 61883 part 6.

2.7.2   Isochronous Data Flow Management

The control of isochronous data flows on the bus shall be done by the concept of plugs and their associated registers which are defined in chapter 7 of IEC 61883-1.
The requirement for the SMASH device are the implementation of an output master plug register and an input master plug register. Since the SMASH device shall support at least one isochronous input stream or one output stream it is necessary to implement at least one output plug control register and one input plug control register.

2.7.3    Connection Management Procedures (CMP)

The management of Isochronous data flow shall be done by procedures which are defined in IEC 61883-1.
Following basic procedures shall be implemented:

Which type of connection used is beyond this specification

2.7.4    Function Control Protocol (FCP)

The FCP is required to send and receive commands for AV devices. It shall be according to IEC 61883 -1 chapter 9. A command and a response register at following addresses are required:
Top address of command register:      FFFF F000 0B00 16
Top address of response register :      FFFF F000 0D00 16
The Command/Transaction Set (CTS) code value shall be 0000 b for AV devices.

2.7.4.1    AV/C Command language

The AV/C command language is currently in the draft standard under development at the 1394 Trade Association, but will be submitted to the IEC.
Following general commands shall be supported:

SUB UNIT INFO
UNIT INFO

Following commands to control a digital VCR (subunit type = 4) shall be supported. These commands perform only basic functionality.

OUTPUT SIGNAL MODE
INPUT SIGNAL MODE

Following values shall be supported

Value (hex) Signal mode
80 SD 625-50
10 MPEG 25 Mbit/s-60
14 MPEG 12,5 Mbit/s-60
18 MPEG 6,25 Mbit/s-60
90 MPEG 25 Mbit/s-50
94 MPEG 12,5 Mbit/s-50
98 MPEG 6,15 Mbit/s-50

           Table 7 Values and Coding for Signal Mode Command

RECORD
The recording mode with the value 75 (recording speed = x1) shall be supported.

PLAY
Only the playback speed x1 (value = 38 16 ) is required

WIND
Following subfunctions are required:

Value (hex) subfunction
60 STOP
65 REWIND
75 FAST FORWARD

            Table 8 Values and Coding for Wind Subfunctions

2.8    Internet Protocol (IP) over IEEE1394

Some SMASH applications are using the Internet Protocol as a Network Layer. This protocol layer shall be kept on the Interconnect System.

The standardization on Internet Protocol over IEEE1394 has not been finalized yet. A working group of the "Internet Engineering Task Force" (IETF) is developing a draft. This encapsulation shall be used when the Internet standard (RFC) becomes available.


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